EE457 - Summer 2017 Computer Systems Organization

Basic RTL design:

  1. DPU and CU

  2. Mealy machine example -- Divider Design

  3. Data registers -- clocking and controlling

  4. Loop Counter Incrementation and Terminal Value Checking

  5. ME (Mutually Exclusive) and AI (All Inclusive) rules in designing a state diagram

  6. State diagram Design examples

Verilog Learning Modules

Verilog HDL:

Six lectures (together with slides) were posted at the link below to introduce the essential aspects of Verilog to the EE354L students (and to the graduate students in EE457, who are new to Verilog coding), so that they can get started with using Verilog for completing their labs. The lectures add up to 3 Hours 40 minutes.

All files

Individual links

1_Verilog_Introduction_mht.jnt

1_Verilog_Introduction.avi (1 H 08 Minutes)

2_module_DataTypes_in_Verilog.jnt

2_module_DataTypes_in_Verilog.avi (23 minutes)

3_behavioral_vs_structural_Verilog.jnt

3_behavioral_vs_structural_Verilog.avi (17 minutes)

4_Sequential_Statements_in_Verilog.jnt

4_Sequential_Statements_in_Verilog.avi (1 Hour)

5_blocking_non_blocking.pdf

5_blocking_non_blocking.avi (56 minutes)

6_RTL_coding_style.jnt

6_RTL_coding_style.avi (33 minutes)

EE201L_RTL_coding_style_verilog.pdf

ee201_divider_simple.zip